AMD's Ryzen 3D V-Cache Chips Have Been in Development For Years

Bolt it on and go

AMD announced its 3D V-Cache technology a few months ago, demonstrating incredible performance gains from simply stacking more L3 cache, up to 64MB, on top of Ryzen CPUs. Now, thanks to Yuzo Fukuzaki from TechInsights, we have more details related to 3D V-Cache. This includes data that shows that modern Zen 3 CPUs were designed to accommodate stacked 3D cache from the start, telling us this technology has been in the works for years.

According to Fukuzaki, he has found connection points, and the space for 3D stacked cache on a standard Ryzen 9 5950X sample. Looking at the picture below, you can see dots along the edges of Zen 3's die where the 3D V-Cache could be connected. These are copper connection points for another stack of 3D cache if it were to be installed.

This installation process uses TSVs (through-silicon vias) via hybrid bonding to secure the second layer of SRAM to the chip. Because TSVs use copper instead of solder, the SRAM has significantly higher bandwidth and thermal efficiency than simply soldering the chips together.

Based on their analysis, the firm has reverse-engineered some of the specifics behind how the 3D V-Cache will be connected, including TSV pitch, the empty space inside the CPU for another stack of cache, and more.

  • TSV pitch ; 17μm
  • KOZ size ; 6.2 x 5.3 μm
  • TSV counts rough estimation ; about 23 thousands!!
  • TSV process position ; Between M10-M11 (15 Metals in total, starting from M0)

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    This all confirms that AMD has been planning to implement 3D V-Cache for quite some time now, so it makes perfect sense that it can release updated Zen 3 parts later this year with significantly more cache thanks to this technology — the company obviously laid the foundation several years ago. 

    It's logical to expect AMD to use 3D V-Cache with its future architectures, too, like the new Zen 4 architecture that is around the corner. 3D V-Cache will give AMD CPUs a huge advantage over Intel in terms of raw L3 cache sizes (at least for now), which are becoming more and more important as CPU core counts increase.

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